|
|
|
|
| Parameter |
Minimum |
Typical |
Maximum |
|
| Frequency
Range |
960
to 1240 |
MHz |
|
| Step
Size |
500 |
KHz |
|
| Frequency
Accuracy |
Ext.
Ref |
|
|
| Ref.
Input Frequency |
10 |
MHz |
HCMOS |
| Settling
Time for any Freq. Hop |
700 |
usec |
within
100 Hz |
| Harmonics
(max) |
-20 |
dBc |
|
| Non-Harmonic
Spurious (max) |
-65 |
dBc |
|
| Phase
Noise @ |
|
|
| 10
KHz |
-80 |
dBc/Hz |
|
| 100
KHz |
-105 |
dBc/Hz |
|
| 1
MHz |
-125 |
dBc/Hz |
note
1 |
| 10
MHz |
-145 |
dBc/Hz |
note
1 |
| Output
Power Level |
10
± 2 |
dBm |
|
| DC
Supply Voltage |
|
|
| VCO |
+12 |
V |
|
| PLL |
+5 |
V |
|
| Charge
Pump |
+12 |
V |
|
| Lock
Detector Output |
TTL |
|
note
2 |
| Control |
3
lines |
|
note
3 |
| Package
Size |
1.05 |
in
sq. |
|
| Temperature |
-20
to +70 |
C |
|
| Humidity
(non-condensing) |
95 |
% |
note
1 |
| Vibration
(10 Hz to 2 KHz) |
5 |
g
rms |
note
1 |
| Shock
(half-sine for 11msec) |
20 |
g's |
note
1 |
| Note |
1: design goal; not tested
in productionNote
2: 0=locked; 1=unlockedNote
3: Data, Clock, Latch Enable |